NPTEL Advanced Computer Architecture Week 6 Assignment Answers 2024

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NPTEL Advanced Computer Architecture Week 6 Assignment Answers 2024

1. The ____________ processors have been replaced by ___________ processors because they guarantee _________. (VLIW – Very Long Instruction Word, EPIC – Explicitly Parallel Instruction Computing).

  • VLIW, EPIC, correctness
  • EPIC, VLIW, correctness
  • VLIW, EPIC, availability
  • EPIC, VLIW, availability
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2. Which of the following is not a part of Intel Itanium processors?

  • Branch predictor
  • Decode unit
  • Instruction window
  • Execute unit
Answer :-  For Answer Click Here 

3. The traditional branch predictor in Intel Itanium is a large ____________ predictor.

  • GAp
  • GAg
  • PAg
  • PAp
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4. Which among the following can be used to deal with data hazards in the Intel Itanium processors?

  • Poison bit
  • Dependence bit
  • Stop bit
  • None of these
Answer :- 

5. Which of the following structures is used by the High Performance Execution Engine of Intel Itanium for selecting the instruction to be issued?

  • Register Stack Engine
  • Scoreboard
  • Functional Unit
  • None of these
Answer :- 

6. In the PLAs, the ___________ plane computes the minterms, and the __________ plane can be used to implement any boolean function.

  • AND, OR
  • NAND, OR
  • AND, XOR
  • NAND, XOR
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7. Which among the following is the correct order of the stages in a graphics pipeline?

  • Vector processor → Pixel engine → Rasteriser → Fragment processor
  • Vector processor → Rasteriser → Fragment processor → Pixel engine
  • Fragment processor → Vector processor → Pixel engine → Rasteriser
  • None of these
Answer :- 

8. Which among the following is a part of Attribute Setup?

  • Computing the depth of each object
  • Breaking down the polygons into triangles
  • Clipping the window to create viewport
  • All of these
Answer :- 

9. Which of the following statements is true regarding NVIDIA’s CUDA toolkit?

  • PTX is a CISC-like instruction set.
  • The dynamic PTX to SASS compilation takes place at compile time.
  • The CUDA command nvcc compiles only the GPU code and not the CPU code.
  • None of these.
Answer :- 

10. A barrier is a __________ within a thread block. Each thread block works _________ the other thread blocks.

  • synchronisation point , independent of
  • termination point , independent of
  • synchronisation point, in synchronisation with
  • termination point, in synchronisation with
Answer :-  For Answer Click Here