NPTEL Advanced Computer Architecture Week 1 Assignment Answers 2024

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NPTEL Advanced Computer Architecture Week 1 Assignment Answers 2024

1. Consider the following statements.

S1: A pipeline bubble refers to an instruction that does not perform any operation.
S2: An interlock inserts a nop instruction in the pipeline.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are false
  • Both S1 and S2 are true
Answer :- For Answer Click Here

2. A situation where there is a risk of executing instructions on the wrong path is called __________ .

  • Data Hazard
  • Control Hazard
  • Structural Hazard
  • Stall
Answer :- For Answer Click Here

3. Which of the following is not a valid forwarding path?

  • RW -> MA
  • MA -> EX
  • EX -> RW
  • RW ->OF
Answer :- For Answer Click Here

4. A technique to pass ___________ between pipeline stages to eliminate _____________ is known as forwarding.

  • results, data hazards
  • results, control hazards
  • signals, data hazards
  • signals, control hazards
Answer :- 

5. Performance of a program is ___________________ to the __________.

  • proportional, the time that the program takes to execute
  • inversely proportional, IPC of the processor
  • proportional, number of dynamic instructions
  • inversely proportional, clock frequency
Answer :- 

6. The IPC of an in-order pipeline is _____ if there are no stalls and _____ otherwise.

  • greater than 1, 1
  • 1, 1
  • 1, less than 1
  • greater than 1, less than 1
Answer :- For Answer Click Here

7. Consider the following statements.

S1: In conventional pipelined processor, performance is higher because we can process more instructions at the same time.
S2: Increasing the number of pipeline stages allows us to increase the clock frequency.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- 

8. Consider the following statements.

S1: If we keep increasing the pipeline stages, the stall penalty (in terms of cycles) will keep decreasing.
S2: Even with infinite number of pipeline stages, the minimum clock period will be limited by the latch delay.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- 

9. Consider the following statements.

S1: Instruction Level Parallelism refers to the number of instructions that can be fetched simultaneously.
S2: Out of order processors don’t always follow data dependence order .

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- 

10. Consider the following statements.

S1: A superscalar processor can execute multiple instructions at a time.
S2: Superscalar processors have multiple out of order pipelines.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- For Answer Click Here